1. Field of the Invention
The present invention relates to a microprocessor, and more particularly to a pipelined microprocessor having exception processing features.
2. Description of the Prior Art
The pipeline system has been widely put to use for improving the processing speed of the microprocessor.
In general, pipelining divides processing for a series of instructions or operations among a plurality of circuits to allow each circuit to sequentially process results simultaneously and in parallel. Pipelining does not reduce the time required to process one instruction or one operation, but reduces the overall processing time substantially in inverse proportion to the divided number of the processing circuits.
Pipelines have experienced difficulties in processing exceptions. An exception, as used herein, means any information whose processing requires a deviation from continuous, sequential processing.
When an exception occurs during pipelining, such as when an error or the like is created, the processor must cancel subsequent pipelining and reexecute the processing from the stage where the exception first occurred. Also, where pipelining is used for instruction processing, when an exception requiring a temporary interruption is encountered such as a branch instruction, various problems will be created. For example, if at a certain stage of pipelining, it is decoded that an instruction under processing is a branch instruction, so that a branch condition is established at the stage executing the decoding, the next instruction to be executed is not the following one but the branched one. Accordingly, it is required that all the following instructions having already started pipelining be canceled and the branched instruction is newly fetched into the first stage of the pipelining and thereafter the processing is reexecuted.
The automatic cancellation approach to exception processing takes additional processing steps, and therefore time, and may cause cancellation of results which are otherwise acceptable.
To further clarify some of the problems attending handling exceptions in connection with pipelined processors, consider the prior art circuit of FIG. 1.
FIG. 1 is a block diagram of the principal portion of a microprocessor having the pipelining function disclosed in the Japanese Patent Laid Open No. 56-92643 (1981).
Referring now to FIG. 1, there is shown a pipelined processor for calculation which includes five stages: an operand readout stage 17, a first calculation stage 18, a second calculation stage 19, a store/exception check stage 20, and an operand store stage 21. Also shown in FIG. 1 are corresponding flip-flops, respectively, reset-set flip-flop 15, D flip-flop 161, D flip-flop 162, D flip-flop 163, and D flip-flop 164 as will be more particularly described hereafter.
Also included in the pipeline at FIG. 1 is an operand counter 27, which, when the remainder is zero, outputs a reset signal at a high level to OR gate 241 through a signal line 23.
Also shown in FIG. 1 is a signal line 14, which conveys a control signal for indicating that processing has started, by giving R-S (reset-set)-flip-flop 15 a processing start signal for starting the calculation.
Referring again to FIG. 1, the output of the R-S-flip-flop 15 is input to the operand readout stage 17 and to a first D flip-flop 161. The output of the first D flip-flop 161 is input to the first calculation stage 18 and a second D flip-flop 162. The output of the second D flip-flop 162 is input to the second calculation stage 19 and a third D flip-flop 163. The output of the third D flip-flop 163 is input to the store/exception check stage 20 and a fourth D flip-flop 164. The output of the fourth D flip-flop 164 is input to the operand store stage 21. In addition, flip-flops 15 and 161 through 164 operate in synchronism with a clock (not shown).
Referring still to FIG. 1, there is shown an interruption priority circuit 22, which, when an exception such as an error is generated, receives as input through signal lines 251, 252, and 253 interruption request signals from the outputs of operand readout stage 17, second calculation stage 19, and store/exception check stage 20. The interruption priority circuit 22 outputs an interruption request signal to a control circuit 26 (not shown) through a signal line 26.
In addition, the aforesaid interruption request signal from the operand readout is coupled to the input of OR gates 241 and 242; the interruption request from calculation stage 19 is coupled to OR gates 241, 242, and 243; and the signal from check stage 20 is coupled to the input of OR gates 241, 242, and 243 and to D flip-flops 163 and 164.
The conventional processing unit of FIG. 1 operates as follows.
The data number for the processing object is set in operand counter 27 simultaneously with the start of pipelining and a processing start signal is given to the R-S-flip-flop 15 from a control circuit (not shown) through a signal line 14. Next, the R-S-flip-flop 15 is set to turn its output to a high level. Hence, the operand readout stage 17 of the first stage of the pipeline becomes active to start processing.
Upon turning the output of R-S-flip-flop 15 to the high level, the flip-flops 161 through 164 are synchronized with the clock so as to be set and develop the high level outputs every one clock cycle, in a lagging sequence. On the other hand, since the respective stages 17 through 21 perform processing between the respective clocks, stages 17 through 21 become active corresponding to the respective flip-flop 15 and 161 through 164 being set sequentially in synchronism with the clock, thereby performing processing in order.
Accordingly, in normal operation, the operand readout stage 17 sequentially fetches the calculation object in synchronism with the clock, the respective stages 17 through 21 sequentially process the calculation object in synchronism with the clock, and the results of processing are sequentially transferred to the next stage. Thereafter, when the operand readout stage 17 processes the last processing object and delivers the result thereof to the first calculation stage 18, the remainder in the operand counter 27 is zero. Accordingly, the reset signal (zero) is output from the operand counter 27 through the signal line 23. R-S-flip-flop 15 is thereby reset and the operand readout stage 17 is inactivated. The following stages 18 through 21 respectively process the last processing object sequentially in synchronism with the clock and the results of processing are sequentially transferred to the next stage in order. Also, as the respective D flip-flops 161 through 164 are reset in lagging sequential order in synchronism with the clock, the respective stages 18 through 21 are sequentially inactivated.
The above operation is under normal processing conditions, but when an exception such as an error is received or generated the operation of the microprocessor is as follows.
When an error occurs at a given stage, the data being processed at the stage where the error is created is cancelled, and the processing results in preceding stages (following processing) which are high in the possibility of generating the error are also cancelled. Cancellation in all such stages is inefficient, however, when, for example, the error is an isolated occurrence at one stage. The processing in succeeding stages ahead of the stage generating the error (preceding processing) is effective, whereby the preceding processing is continued until it reaches the last stage in the pipeline.
Referring again to FIG. 1, when an error occurs, an interruption request signal 251, 252, and 253 is output from either one of the operand readout stage 17, second calculation stage 19, or store/exception check stage 20, and the flip-flop corresponding to the interruption request signal, and that at preceding stages are reset. Simultaneously, the interruption request signal is input to the interruption priority circuit 22 and supplied to the control circuit (not shown) through the signal line 26.
When the control circuit accepts the interruption, all following pipelining will be reexecuted on the basis of set/reset (level of output signal) of the flip-flops 15 and 161 through 164 and an obtained count of the operand counter 27. Thus, in order to process exceptions, set/reset signals must be conveyed to the external control circuit, the external control circuit must accept the interruption, and the nature of the error and the proper response must be determined by the control circuit. Further, as shown in FIG. 1, the stage which checks for exceptions is a separate stage at the end of the pipeline.
In addition, when an error is generated simultaneously at a plurality of stages, the flip-flops corresponding to the most advanced stage and all preceding stages are all reset and the interruption priority circuit 22 decides the interruption priority. All processing following the stage where the error occurred is automatically cancelled.
Moreover, a problem occurs in implementing a control circuit for the processor in FIG. 1 in that as the number of stages for the pipeline increases, the program and circuitry for control become complicated and large-scale. In addition, additional delay is created because signals must be conveyed to and received from the complicated external control circuit which must also determine the source of the exception, the kind of exception, and the proper response.
The aforesaid prior art is exemplary of pipelining for calculation, but besides this, the Japanese Patent Laid-Open No. 57-29155 (1982) discloses an example of pipelining for instruction processing.
From the foregoing, it can be seen that what is needed when an exception occurs during pipelined processing is a means to delay cancellation or reexecution by the pipeline until after the entire preceding instruction groups in advance complete execution, and the error can be properly analyzed and isolated.
What is also needed is a simple method for indicating the stage of the pipeline at which the exception occurred and for controlling cancellation and reexecution of processing such that circuit complexity, delay, decision, and reexecution time is kept to a minimum.